Memory Technologies, Storage & Software Architecture

Fundamentals of Computer Science · Unit 2

Unit 2 — Memory Technologies, Storage Ecosystem & Software Architecture

1. Primary Semiconductor Memory: RAM & ROM

Computer memory stores binary instructions and data for processing by the CPU. Primary memory communicates directly with the processor via the internal system bus.

                                  PRIMARY MEMORY
                                        |
                 +----------------------+----------------------+
                 |                                             |
             RAM (Volatile)                             ROM (Non-Volatile)
                 |                                             |
         +-------+-------+                      +-------+------+------+-------+
         |               |                      |       |      |      |       |
       SRAM            DRAM                   Mask    PROM   EPROM  EEPROM  Flash

1.1 Random Access Memory (RAM)

RAM is the system's volatile working memory; any word can be accessed in constant time $$O(1)$$ regardless of its physical location on the chip.

SRAM vs. DRAM: In-Depth Technical Comparison

Technical Parameter	Static RAM (SRAM)	Dynamic RAM (DRAM)
Storage Element	Flip-flop circuit composed of 4 to 6 transistors per bit cell.	Single capacitor paired with 1 access transistor per bit cell.
Retention Mechanism	Data remains stable as long as DC power is supplied; no charge leakage.	Stored as an electrical charge in a capacitor; leaks charge rapidly over time.
Refresh Requirement	No refresh required.	Periodic refreshing required (thousands of times per second) via refresh cycles.
Access Time / Speed	Extremely fast: $1\text{ to }10\text{ ns}$ . Matches CPU cycle speed.	Moderately fast: $50\text{ to }70\text{ ns}$ . Slower due to capacitive charging/discharging.
Physical Density	Low density: Large cell footprint (6 transistors take more silicon die area).	High density: Very compact cell footprint (1 transistor + 1 capacitor).
Cost per Bit	High cost per gigabyte.	Low cost per gigabyte.
Power Consumption	Low dynamic power during idle; higher power under continuous operation.	Higher continuous power due to mandatory refresh operations.
Primary System Use	CPU Cache Memory (L1, L2, L3 caches) and CPU internal registers.	Main System Memory (DDR4 / DDR5 RAM sticks) in PCs, laptops, and servers.

1.2 Read-Only Memory (ROM)

ROM stores permanent instructions required during the initial bootstrap of the computer. It is non-volatile: data persists when the power supply is severed.

Classification of ROM Types

Mask ROM (MROM):
- Hardwired during physical integrated-circuit fabrication by the manufacturer.
- Cannot be modified or updated after manufacturing. Inexpensive only in mass-production runs.
PROM (Programmable ROM):
- Shipped blank with tiny internal fuses.
- Programmed once by the user or vendor using a specialized hardware device called a PROM Programmer (burning fuses). Once programmed, it can never be rewritten (WORM: Write Once, Read Many).
EPROM (Erasable Programmable ROM):
- Can be erased and reprogrammed multiple times.
- Erasure Mechanism: The chip features a circular quartz crystal window on its package. Exposing the quartz window to intense Ultraviolet (UV) light for 20–30 minutes clears all stored charges, restoring the chip to an unprogrammed state. Must be removed from the motherboard for erasure.
EEPROM (Electrically Erasable Programmable ROM):
- Erased and rewritten electrically without removing the chip from the circuit board.
- Erases data byte-by-byte, making updates flexible but comparatively slow.
Flash Memory:
- An advanced, high-performance variant of EEPROM.
- Key Distinction: Rather than byte-by-byte operations, Flash memory erases and writes data in entire blocks or sectors (typically 512 bytes to 4KB), achieving vastly superior write throughput.
- Forms the basis of modern motherboard UEFI/BIOS firmware, USB pendrives, and SSDs.

2. Secondary Storage Ecosystem: HDD, SSD, NVMe & Optical

Secondary storage provides high-capacity, permanent, non-volatile data retention for operating systems, application suites, and user files.

                          SECONDARY STORAGE SPECTRUM
   [ Magnetic (HDD) ] ---------> [ SATA SSD ] ---------> [ NVMe PCIe SSD ]
   Moving Mechanical Parts        Flash Chips (SATA Bus)   Flash Chips (Direct PCIe)
   Speed: ~150 MB/s               Speed: ~550 MB/s         Speed: 3500 - 7000+ MB/s
   Latency: ~10 ms (Mechanical)   Latency: ~0.1 ms         Latency: ~0.02 ms

2.1 Hard Disk Drives (HDD) — Magnetic Storage

An HDD records binary bits by magnetizing microscopic domains on spinning circular magnetic platters.

Physical Anatomy:
- Platters: Rigid magnetic-coated disks rotating around a central spindle at high speeds (typically 5400 RPM or 7200 RPM).
- Read/Write Heads: Aerodynamic electromagnetic sensors floating nanometers above the platter surfaces on an actuator arm.
- Tracks: Concentric circular rings across platter surfaces.
- Sectors: Pie-shaped slices dividing each track; the smallest addressable unit of disk storage (historically $512\text{ bytes}$ , modern Advanced Format uses $4096\text{ bytes}$ ).
- Cylinder: The vertical alignment of all tracks across multiple stacked platters at a given head position.
Latency Factors:
- Seek Time: The time required for the actuator arm to physically move the read/write head to the targeted track/cylinder.
- Rotational Latency: The time spent waiting for the targeted sector to spin beneath the read/write head ( $\text{Average} = \frac{1}{2} \times \text{time of one revolution}$ ).
- Transfer Rate: The rate at which data bits are sequentially read from magnetic medium into memory.

2.2 Solid State Drives (SSD) — Semiconductor Storage

SSDs contain no moving parts; they store data across interconnected NAND Flash memory chips orchestrated by an intelligent microcontroller.

NAND Cell Technologies:
- SLC (Single-Level Cell): 1 bit per cell. Highest endurance ( $100,000\text{ write cycles}$ ), highest speed, highest cost.
- MLC (Multi-Level Cell): 2 bits per cell. Good endurance ( $10,000\text{ cycles}$ ).
- TLC (Triple-Level Cell): 3 bits per cell. Standard consumer SSD standard ( $3,000\text{ cycles}$ ).
- QLC (Quad-Level Cell): 4 bits per cell. High capacity, lowest write endurance ( $1,000\text{ cycles}$ ).
Core SSD Controller Functions:
- Wear Leveling: Intelligently distributes write/erase cycles evenly across all memory blocks to prevent premature degradation of localized cells.
- TRIM Command: An OS-level ATA command informing the SSD which data blocks are no longer in use, allowing the drive to wipe them in the background for rapid subsequent writes.
- Garbage Collection: Consolidating valid data from partially filled blocks so older blocks can be completely erased.

2.3 HDD vs. SSD: Comprehensive Comparison

Feature	Hard Disk Drive (HDD)	Solid State Drive (SSD)
Operating Mechanism	Electromechanical: spinning magnetic platters + moving heads.	Pure solid-state: electronic NAND flash memory chips.
Sequential Read/Write Speed	$100\text{ to }200\text{ MB/s}$	$500\text{ to }7,000+\text{ MB/s}$ (SATA to NVMe Gen4).
Random Access Latency	$5\text{ to }15\text{ ms}$ (constrained by mechanical inertia).	$0.02\text{ to }0.1\text{ ms}$ (instantaneous electronic access).
Input/Output Operations (IOPS)	$\sim 100\text{ to }200\text{ IOPS}$	$50,000\text{ to }1,000,000+\text{ IOPS}$
Physical Durability	Vulnerable to head crashes and damage from physical drops or shock.	Highly durable; immune to vibration, drops, and magnetic fields.
Noise & Power	Generates audible spinning hum and vibration; higher wattage.	Completely silent; draws significantly less power.
Cost per Gigabyte	Very economical for massive data archiving ( $4\text{TB to }20\text{TB}$ ).	More expensive per gigabyte; ideal for OS and active software.

2.4 Interface Protocols: SATA vs. NVMe

SATA III (Serial ATA): Legacy storage bus designed originally for spinning hard drives. Bottlenecked at a maximum theoretical bandwidth of $6\text{ Gbps}$ ( $\approx 550\text{ MB/s}$ ) through the AHCI driver stack.
NVMe (Non-Volatile Memory Express): Modern storage protocol designed ground-up for high-speed flash. Connects directly over the PCIe (Peripheral Component Interconnect Express) bus, utilizing multiple high-speed lanes (e.g., PCIe 4.0 x4 provides bandwidth up to $7,500\text{ MB/s}$ ) with massive parallel queue depths (64,000 queues of 64,000 commands).

2.5 Optical Storage Media

Optical drives store data as microscopic pits (indentations) and lands (flat areas) read by a reflected laser beam:

CD (Compact Disc): Uses a $780\text{ nm}$ infrared laser; standard capacity $700\text{ MB}$ .
DVD (Digital Versatile Disc): Uses a $650\text{ nm}$ red laser (tighter pit spacing); capacity $4.7\text{ GB}$ (single layer) to $8.5\text{ GB}$ (dual layer).
Blu-ray Disc (BD): Uses a $405\text{ nm}$ short blue-violet laser allowing extreme data density; capacity $25\text{ GB}$ (single layer) to $50\text{ GB}$ (dual layer).

3. Software Classification & Architecture

Software comprises the entire collection of programs, procedures, and documentation that instruct computer hardware on how to execute tasks.

                                  COMPUTER SOFTWARE
                                          |
                 +------------------------+------------------------+
                 |                                                 |
          SYSTEM SOFTWARE                                 APPLICATION SOFTWARE
                 |                                                 |
         +-------+-------+                                 +-------+-------+
         |               |                                 |               |
     Operating        Device       Utility              General         Bespoke /
      Systems        Drivers      Software              Purpose        Tailored

3.1 Software Categories

System Software:
- Controls internal computer operations and provides an abstraction platform over physical hardware for application programs.
- Components: Operating Systems (Windows, Linux, macOS), Device Drivers (display adapter driver, audio driver), and Language Translators.
Application Software:
- Programs designed to help end users perform specific productivity, entertainment, or academic tasks.
- General Purpose: Word processors (MS Word), Web browsers (Chrome), Spreadsheets (Excel).
- Special Purpose / Bespoke: Custom banking portals, university attendance systems, hospital patient management software.
Utility Software:
- System maintenance tools designed to optimize, analyze, and protect computer resources.
- Examples: Disk Defragmenter, Antivirus software (Windows Defender), Disk Cleanup, File Compression utilities (WinRAR, 7-Zip).
Middleware:
- "Software glue" that connects disparate software applications or components, enabling distributed communication over networks (e.g., database connectors like ODBC/JDBC, message brokers like RabbitMQ).

4. Programming Languages & Language Translators

A programming language is a formal notation used to develop instructions for computers.

4.1 Generations of Programming Languages

Generation	Classification	Defining Characteristics	Examples
1st Gen (1GL)	Machine Language	Written entirely in raw binary code (`0`s and `1`s). Executed directly by hardware with zero translation. Difficult for humans to write, debug, and entirely hardware-dependent.	Binary opcodes (`10110000 01100001`)
2nd Gen (2GL)	Assembly Language	Replaces binary numbers with human-readable symbolic mnemonics (`MOV`, `ADD`, `SUB`, `JMP`) and register labels. Machine-dependent; requires an Assembler.	NASM, MASM, x86 Assembly
3rd Gen (3GL)	High-Level Languages	Uses English-like keywords, algebraic expressions, and structured flow controls (`if`, `while`). Machine-independent (portable across architectures).	C, C++, Java, Pascal, Fortran
4th Gen (4GL)	Declarative Languages	Focuses on "what to do" rather than step-by-step "how to do it". Highly concise; frequently used for database manipulation and reporting.	SQL, MATLAB, PL/SQL
5th Gen (5GL)	AI & Constraint Languages	Problem-solving based on constraints and logical rules rather than explicit procedural algorithms.	Prolog, LISP, Mercury

4.2 Language Translators: Assembler, Compiler, Interpreter

Because CPU hardware can exclusively interpret binary machine code, all programs written in assembly or high-level languages must be translated before execution.

Assembly Code    ----[ Assembler ]----> Machine Code (0s & 1s)
Source Code (C)  ----[ Compiler ]-----> Object Code / Executable (.exe) ---> Direct Execution
Source Code (Py) ----[ Interpreter ]---> Line-by-Line Translation & Immediate Execution

Detailed Comparison of Language Translators

Parameter	Assembler	Compiler	Interpreter
Input Language	Assembly Language (2GL).	High-Level Language (C, C++, Rust).	High-Level Language (Python, Ruby, JavaScript).
Translation Unit	Translates mnemonics directly into machine instructions.	Scans and translates the entire program all at once.	Translates and executes the source program line-by-line.
Intermediate Object Code	Generates an object file (`.o` / `.obj`).	Generates independent object / executable file (`.exe`).	No intermediate object file produced. Executes directly in memory.
Execution Speed	Very fast.	Extremely fast runtime execution (CPU runs compiled binary directly).	Slower runtime execution (every line must be parsed repeatedly during loops).
Memory Requirement	Low memory footprint.	High initial memory during compilation; zero compiler memory needed during runtime execution.	Interpreter must remain resident in memory throughout the entire execution.
Error Reporting	Reports syntax errors during assembly pass.	Scans entire file; presents a comprehensive list of all syntax errors after compilation pass.	Halts execution immediately at the very first syntax/runtime error encountered.
Code Modification	Requires re-assembly.	Any source change requires re-compilation of the source code.	Highly interactive; changes can be tested immediately without a separate compilation step.

4.3 Hybrid Execution Systems (Java & Python)

Modern languages often blend compilation and interpretation for cross-platform portability:

Java Virtual Machine (JVM): The Java compiler (javac) translates source code into architecture-neutral Bytecode (.class files). The Java Virtual Machine (JVM) interprets bytecode on the target machine, utilizing a Just-In-Time (JIT) Compiler to compile hot loops directly into native machine code at runtime for near-native speed.

5. Firmware & Bootstrapping Architecture

Firmware is permanent, low-level software programmed directly into non-volatile memory chips (such as Flash EEPROM) during hardware manufacturing. It provides the initial operational environment for computing hardware before any operating system is loaded.

5.1 BIOS vs. UEFI

Feature	Legacy BIOS (Basic Input/Output System)	Modern UEFI (Unified Extensible Firmware Interface)
Architecture	16-bit real-mode execution; limited to $1\text{ MB}$ address space.	32-bit or 64-bit protected mode; access to full system memory.
Partition Table Scheme	MBR (Master Boot Record): Max disk size $2.2\text{ TB}$ ; max 4 primary partitions.	GPT (GUID Partition Table): Max disk size $9.4\text{ ZB}$ ; supports up to 128 primary partitions.
Boot Speed	Slower; sequential hardware component polling.	Much faster; parallel hardware initialization.
Security Features	No native cryptographic validation of boot binaries.	Secure Boot: Cryptographically checks digital signatures of OS loaders to prevent rootkits.
User Interface	Text-based, keyboard-only blue terminal screens.	Graphical user interface with mouse support, animations, and network configuration.

5.2 The Computer Boot Process (Step-by-Step)

[ 1. Power-On ] -> [ 2. CPU Reset ] -> [ 3. POST Check ] -> [ 4. Firmware Init ] -> [ 5. Bootloader (GRUB/Windows) ] -> [ 6. OS Kernel Loaded ]

Power-On & Power Good Signal: The Power Supply Unit (PSU) stabilizes electrical voltages and sends a "Power Good" signal to the motherboard clock generator.
CPU Reset: The CPU resets its registers and automatically initializes its Program Counter (PC) to point to the fixed memory address where firmware code begins (typically 0xFFFF0).
POST (Power-On Self-Test): The firmware conducts diagnostic hardware checks:
- Verifies CPU registers, tests RAM integrity, scans internal system buses, checks keyboard connectivity, and initializes display hardware.
- If a critical hardware failure occurs, the firmware issues diagnostic beep codes or motherboard LED error codes.
Hardware Initialization: Firmware sets interrupt tables, checks storage drives, and locates the designated boot device based on the user's configured Boot Priority Order.
Bootstrap Loader Execution: The firmware reads the primary boot sector (MBR or EFI System Partition) into RAM and transfers CPU control to the secondary bootloader (e.g., Windows Boot Manager or GRUB for Linux).
Operating System Loading: The bootloader loads the operating system kernel into memory, mounts the root filesystem, initializes device drivers, and launches system services into user space.

6. Unit 2 Review & CAT 2 Exam Checklist

SRAM vs. DRAM: Be prepared to draw the flip-flop vs capacitor/transistor distinction and list 4 major engineering differences.
ROM Generations: Explain the erasure mechanisms of PROM (fuses), EPROM (UV light), and EEPROM/Flash (electrical).
HDD vs. SSD: Memorize the mechanical latency factors of HDDs (seek time + rotational latency) and explain why SSDs provide superior random access IOPS.
SATA vs. NVMe: Contrast bus limits ( $6\text{Gbps}$ vs PCIe lanes) and command queue depths.
Translators: Write the definitive comparison table between Compilers, Interpreters, and Assemblers.
BIOS vs. UEFI: State disk size limits ( $2.2\text{TB}$ MBR vs GPT) and explain the role of Secure Boot.
POST & Boot Process: Trace the 6-stage lifecycle from power button press to operating system initialization.