Von Neumann Architecture & Practice MCQs

Von Neumann Architecture & Practice MCQs

Course: Fundamentals of Computer Science
Course code: 26CSE0107
Module Type: Topic Spotlight & Thematic Question Set
Coverage: Deep dive into John von Neumann's stored-program architecture, CPU registers, instruction cycle, memory communication pathways, the Von Neumann bottleneck, and 30 categorized practice MCQs.

Contents

1. Architectural foundations and stored-program concept
2. CPU structure and internal registers
3. The instruction execution cycle
4. System buses and memory communication
5. The Von Neumann bottleneck and cache mitigation
6. Categorized examination practice MCQs (Questions 1–30)
7. Unit 1 companion modules

1. Architectural foundations and stored-program concept

The Von Neumann architecture is the theoretical foundation of almost all general-purpose digital computers. Proposed by mathematician and physicist John von Neumann in 1945, it introduced the revolutionary stored-program concept.

[!DEFINITION] In a stored-program computer, both program instructions and user data share a single, common read-write memory space and are transferred over common communication lines.

1.1 Fixed-Program vs. Stored-Program Computers

Prior to the Von Neumann architecture, early electronic machines were fixed-program computers:

1.2 Core Architectural Principles

1. Shared Main Memory: A single unified physical memory address space holds both data values and instruction bit patterns.
2. Sequential Execution: Instructions are normally fetched and executed one after another in strictly sequential numerical order, unless modified by a jump or branch instruction.
3. Control Unit Coordination: A centralized Control Unit (CU) interprets instructions and directs the flow of data between the ALU, registers, and memory.
4. Binary Data Representation: All instructions and numbers are encoded in binary form (0s and 1s).

2. CPU structure and internal registers

The Central Processing Unit (CPU) is the core computational engine. In the Von Neumann model, it contains two primary operational blocks and dedicated high-speed storage registers:

2.1 Major CPU Blocks

• Arithmetic Logic Unit (ALU): Performs arithmetic computations (addition, subtraction, multiplication) and logical evaluations (AND, OR, NOT, comparisons).
• Control Unit (CU): Decodes fetched instructions and generates micro-level timing and control signals that coordinate the ALU, memory, and I/O devices.

2.2 Core Internal Registers

Registers are small, extremely high-speed memory cells embedded directly inside the CPU:

3. The instruction execution cycle

The Von Neumann architecture operates in a continuous hardware loop known as the Instruction Cycle:

   +-------------------------------------------------------+
   |                  Instruction Cycle                    |
   |                                                       |
   |   [1. FETCH]  -->  [2. DECODE]  -->  [3. EXECUTE]     |
   |        ^                                    |         |
   |        +----------- [4. STORE/REPEAT] <-----+         |
   +-------------------------------------------------------+

1. Fetch Step:
   • The CPU sends the address stored in the Program Counter (PC) to the memory via the MAR.
   • The memory returns the instruction code via the MDR, which is loaded into the Instruction Register (IR).
   • The Program Counter (PC) is incremented to point to the next instruction address.
2. Decode Step:
   • The Control Unit (CU) examines the bit pattern in the IR to determine the operation to be performed and identifies operand addresses.
3. Fetch Operands (if required):
   • If the instruction requires data values from memory, memory read cycles are triggered to place those operands into registers.
4. Execute Step:
   • The ALU or execution logic executes the requested operation (e.g., adding two numbers or evaluating a comparison).
5. Store / Place Result:
   • The computed output is written back to the Accumulator, a register, or a specified memory location.
6. Repeat:
   • The cycle restarts with the next instruction pointed to by the PC.

4. System buses and memory communication

Communication between the CPU, main memory, and I/O devices occurs via a shared set of electrical parallel signal lines called the System Bus:

1. Data Bus (Bidirectional):
   • Carries actual data words and instruction opcodes between CPU, memory, and devices.
   • Width determines word size: An 8-bit bus transfers 1 byte at a time; a 64-bit bus transfers 8 bytes simultaneously.
2. Address Bus (Unidirectional):
   • Carries memory addresses from the CPU to main memory.
   • Width determines maximum addressable memory capacity: An $n$-bit address bus addresses $2^n$ unique locations ($16\text{ bits} \implies 64\text{ KB}$, $20\text{ bits} \implies 1\text{ MB}$).
3. Control Bus (Bidirectional / Multiple Control Lines):
   • Carries timing pulses and read/write control signals (e.g., Memory Read, Memory Write, I/O Read, Clock, Reset).

5. The Von Neumann bottleneck and cache mitigation

Because instructions and data must travel across the same shared system bus to and from a single memory:

[!WARNING] The Von Neumann Bottleneck:
The CPU cannot read an instruction and read/write program data simultaneously. Because modern CPU processing speeds increase significantly faster than memory communication bandwidth, the shared memory bus becomes a critical performance bottleneck, forcing the CPU to spend valuable idle cycles waiting for data transfers.

Modern Architectural Solutions:

1. Cache Memory (L1, L2, L3): Small, ultra-fast SRAM placed on or near the processor chip to keep frequently referenced instructions and data immediately accessible, reducing memory bus traffic.
2. Harvard Architecture Separation: Modern microcontrollers and internal L1 CPU caches often separate instruction cache and data cache pipelines, allowing concurrent instruction fetch and data access.
3. Pipelining & Pre-fetching: Fetching subsequent instructions into an instruction pre-fetch queue while current instructions are executing.

6. Categorized examination practice MCQs (Questions 1–30)

6.1 Set A: Architectural Foundations & Pioneers (Questions 1–10)

Q1. The Von Neumann architecture was proposed by:

• A) Charles Babbage
• B) John von Neumann
• C) Alan Turing
• D) Dennis Ritchie

Answer: B) John von Neumann

Q2. The Von Neumann architecture uses a common memory for:

• A) Only data
• B) Only instructions
• C) Instructions and data
• D) Only output

Answer: C) Instructions and data

Q3. The main processing unit in a computer is the:

• A) RAM
• B) CPU
• C) Hard disk
• D) Keyboard

Answer: B) CPU

Q4. CPU stands for:

• A) Central Processing Unit
• B) Computer Processing Utility
• C) Central Program Unit
• D) Computer Program Unit

Answer: A) Central Processing Unit

Q5. The ALU performs:

• A) Input operations
• B) Arithmetic and logical operations
• C) Printing operations
• D) Storage operations only

Answer: B) Arithmetic and logical operations

Q6. The Control Unit mainly:

• A) Stores files permanently
• B) Controls and coordinates computer operations
• C) Displays output
• D) Performs only addition

Answer: B) Controls and coordinates computer operations

Q7. Which component stores instructions and data in Von Neumann architecture?

• A) Memory
• B) Monitor
• C) Keyboard
• D) Printer

Answer: A) Memory

Q8. Which unit is used to enter data into a computer?

• A) Output unit
• B) Input unit
• C) ALU
• D) Control unit

Answer: B) Input unit

Q9. Which unit displays or produces processed results?

• A) Input unit
• B) Memory unit
• C) Output unit
• D) Control unit

Answer: C) Output unit

Q10. A CPU generally contains:

• A) ALU and Control Unit
• B) Keyboard and Mouse
• C) Monitor and Printer
• D) Hard disk and SSD

Answer: A) ALU and Control Unit

6.2 Set B: Instruction Cycle, Sequencing & CPU Registers (Questions 11–20)

Q11. In Von Neumann architecture, instructions are normally executed:

• A) Randomly
• B) Sequentially
• C) Only simultaneously
• D) Without memory

Answer: B) Sequentially

Q12. The first step in the instruction cycle is generally:

• A) Execute
• B) Decode
• C) Fetch
• D) Store

Answer: C) Fetch

Q13. During the fetch step, the CPU:

• A) Gets an instruction from memory
• B) Prints the result
• C) Deletes the instruction
• D) Turns off the computer

Answer: A) Gets an instruction from memory

Q14. During decoding, the CPU determines:

• A) The monitor size
• B) The operation specified by the instruction
• C) The keyboard type
• D) The storage capacity

Answer: B) The operation specified by the instruction

Q15. During execution, the CPU:

• A) Performs the required operation
• B) Only fetches data
• C) Only stores instructions
• D) Turns off memory

Answer: A) Performs the required operation

Q16. Which register usually holds the address of the next instruction?

• A) Accumulator
• B) Program Counter
• C) Instruction Register
• D) Memory Data Register

Answer: B) Program Counter

Q17. The Instruction Register stores:

• A) The current instruction
• B) The next memory address only
• C) Output data permanently
• D) User passwords

Answer: A) The current instruction

Q18. Which component connects the CPU and memory for transferring information?

• A) System bus
• B) Keyboard
• C) Monitor
• D) Printer

Answer: A) System bus

Q19. The three basic types of buses are:

• A) Input, Output, Memory
• B) Data, Address, Control
• C) RAM, ROM, Cache
• D) ALU, CU, Register

Answer: B) Data, Address, Control

Q20. One major feature of Von Neumann architecture is:

• A) Separate memory for instructions and data
• B) Shared memory for instructions and data
• C) No CPU
• D) No memory

Answer: B) Shared memory for instructions and data

6.3 Set C: System Buses, Bottleneck & Caching Analysis (Questions 21–30)

Q21. A processor repeatedly spends significant time transferring instructions and data through the same memory path. This situation is most closely associated with:

• A) Harvard architecture
• B) Von Neumann architecture
• C) Distributed architecture
• D) Parallel architecture

Answer: B) Von Neumann architecture

Q22. A program contains an instruction stored at memory location 500. The Program Counter contains 500 before the fetch operation. After fetching the instruction, the PC will normally:

• A) Remain permanently at 500
• B) Point to the next instruction
• C) Store the instruction itself
• D) Store the execution result

Answer: B) Point to the next instruction

Q23. Consider the sequence: Fetch → Decode → Execute. The primary purpose of the decode stage is to:

• A) Transfer the final result to output
• B) Identify the operation and required operands
• C) Increase the memory capacity
• D) Permanently store the program

Answer: B) Identify the operation and required operands

Q24. A Von Neumann system has one memory containing both instructions and data. If the CPU needs to fetch an instruction while simultaneously accessing data through the same memory interface, the main limitation is:

• A) Lack of ALU
• B) Von Neumann bottleneck
• C) Lack of input devices
• D) Absence of registers

Answer: B) Von Neumann bottleneck

Q25. Which sequence correctly represents the basic instruction cycle?

• A) Execute → Fetch → Decode
• B) Decode → Execute → Fetch
• C) Fetch → Decode → Execute
• D) Fetch → Execute → Decode

Answer: C) Fetch → Decode → Execute

Q26. An instruction requires data from memory before execution. Which sequence best represents the operation?

• A) Fetch instruction → Decode → Fetch required data → Execute
• B) Execute → Decode → Fetch instruction
• C) Decode → Output → Fetch instruction
• D) Fetch data → Delete instruction → Execute

Answer: A) Fetch instruction → Decode → Fetch required data → Execute

Q27. Suppose the CPU has fetched an instruction from memory and placed it in the Instruction Register. The next major step is:

• A) Changing the Program Counter into the ALU
• B) Decoding the instruction
• C) Sending the instruction directly to the printer
• D) Clearing the memory

Answer: B) Decoding the instruction

Q28. A computer uses a single memory space for both program instructions and user data. A program attempts to modify a value stored in its instruction area. This behavior is possible in the basic Von Neumann model because:

• A) Instructions and data use separate memories
• B) Instructions and data share the same memory
• C) CPU has no control unit
• D) ALU permanently stores programs

Answer: B) Instructions and data share the same memory

Q29. Which statement best explains the Von Neumann bottleneck?

• A) CPU cannot perform arithmetic operations
• B) Limited communication bandwidth between CPU and shared memory can restrict performance
• C) RAM cannot store instructions
• D) Input devices operate slower than printers

Answer: B) Limited communication bandwidth between CPU and shared memory can restrict performance

Q30. A processor improves performance by using cache memory close to the CPU while retaining the Von Neumann model. The main purpose of the cache is to:

• A) Eliminate the need for instructions
• B) Reduce the average time required to access frequently used instructions and data
• C) Replace the ALU
• D) Separate all instructions from data permanently

Answer: B) Reduce the average time required to access frequently used instructions and data

7. Unit 1 companion modules

Explore the other dedicated modules in Unit 1:

• Module 01: Computer Fundamentals & Architecture (Core Theory)
• Module 03: Comprehensive MCQ Examination Bank
• Module 04: Linux Lab Practicals & Commands Manual